Huawei’s new patent application, which describes achieving 2nm-class production using only DUV lithography equipment, clearly demonstrates the company’s commitment to pursuing advanced chip production under sanctions.
Huawei Files New Chip Patent
Unable to access ASML’s advanced systems due to extensive export restrictions on EUV machines, Huawei, along with its manufacturing partner SMIC, has nevertheless outlined a production path that pushes the limits of existing infrastructure. Although the patent was filed in 2022, it was recently made public and discovered by semiconductor researcher Dr. Frederick Chen.
The document describes an advanced multi-patterning technique that could enable Huawei and SMIC to achieve a metallographic gap of 21nm. This size is on par with EUV-based 2nm-class processes from TSMC and Samsung.
At the heart of Huawei’s approach is an optimized “Self-Aligned Quad-Layer Patterning” process. While similar techniques in the industry require significantly more exposures, this method reduces the number of DUV exposures to as little as four.
This simplified structure enables an aggressive patterning process while simultaneously pushing the capacity of the DUV infrastructure to the extreme. With this method, the company plans to leapfrog SMIC’s N+3 process, used in the Kirin 9030, directly to the 2nm generation, eliminating the need for EUV tools.
However, industry experts are cautious about the process from a commercial perspective. While feasible in a laboratory setting, such dense multi-patterning is known to reduce yields, increase the risk of errors, and increase costs.
For this reason, leading manufacturers have long since switched to single-exposure EUV for processes at 3nm and below. However, if Huawei’s SAQP-based production reaches high-volume production, it will represent a significant technological breakthrough in the face of sanctions.
The patent demonstrates the company’s commitment to this field and its willingness to push existing lithography technologies in line with China’s goal of reducing external dependence on its semiconductor ecosystem.
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