TSMC shared its developments and plans for 2nm technology at the 2024 North American Technology Symposium. The company introduced NanoFlex, a new technology for 2nm generations, and announced that the 2nd generation of 2nm-class N2P would not include the previously announced backside power delivery network. Here are the details:

TSMC’s NanoFlex technology and changes to N2P’s features

TSMC’s new N2 manufacturing technology promises a 10-15% performance boost and 25-30% lower power consumption compared to the current N3E process. Additionally, the transition to the N2 generation is expected to increase chip density by approximately 1.15 times. The N2 family from TSMC will include at least three generations: the base N2, the performance-focused N2P, and the high-performance N2X.

TSMC’s NanoFlex technology allows chip designers to mix and match high-performance, low-power, and high-density standard cells within the same block, offering greater flexibility in optimizing performance and power consumption. However, the omission of the backside power delivery network from N2P shifts this advanced power delivery to future generations.

Another significant improvement in the N2 generation is the integration of the super high-performance metal-insulator-metal (SHPMIM) capacitor. This new capacitor doubles the capacitance density while reducing resistance by 50% compared to the previous super high-density metal-insulator-metal (SHDMIM) capacitor. This enhances stability in power delivery, allowing for optimized performance and power consumption.

TSMC’s 2nm generations promise significant advances in chip manufacturing with potential impacts in areas like artificial intelligence. These changes could set new technological standards in the chip industry. Feel free to share your thoughts in the comments below.